The scaling of wafer probes to finer pitch presents challenges, as the cost and complexity of wafer probe technology increases. By way of example, in existing approaches, challenges in probe tips include scalability, material selection flexibility, and cost of fabrication. Conventional probe card and probe tip technologies have been extended to cover area array interconnection pitches down to the range 150-200 microns. However, there is demand for probing solutions for area array pitches 50 microns and smaller, solutions which are difficult to achieve with existing approaches. Furthermore, there is a need for fine-pitch probing solutions for three-dimensional silicon device structures.